The present invention relates to logical integrated circuit (IC) and system LSI chips that are constructed by assembling a plurality of logical blocks into a chip, a method of designing such chips and a method of mass production thereof.
When designing logical IC and system LSI chips, such a design method has conventionally been used that comprises dividing the whole functionalty into multiple functional blocks, designing each block, and assembling all blocks into the chip. A design method reusing functional blocks that have been designed beforehand and retained as Intellectual Properties (IPs) has lately been known. A corporation manufacturing IC and LSI chips may buy such blocks of IPs of another corporation in addition to using in-house designed IPs.
When constructing a system LSI chip by assembling its functional blocks into the chip, it is required for each block that signal inputs and outputs take place in conformity with the block interface specifications to make the functional block properly function, wherein the interface means passing input/output signals from one block to another block and vice versa. As a method of determining whether inputting and outputting signals to/from each functional block conform to the interface specifications, the following method is known. To a logic simulation model for a system LSI as a whole, a block is added that monitors input/output signals to/from each functional block and determines whether they occur at correct timing, according to the specifications, during the logic simulation. When the logic simulation model runs, the above determination is made.
Meanwhile, there exists a method of describing the interface specifications of functional blocks, for example, the one disclosed in Japanese Patent Laid-Open Publication (Kokai) No. 2000-123064. In this method disclosed, alphabets are assigned to values of signals in combinations passing across a functional block interface and the interface is defined as a set of sequences of alphabets. As the notation of a sequence and the notation of a set of sequences thereof, regular exprssion is used so that a variety of interface definitions can be described by a small quantity of code. Hereinafter, this notation will be referred to as interface notation of Kokai 2000-123064.
As methods for detecting defective or faulty LSIs due to errors in the fabrication process or after the fabrication, a Build-In Self Test (BIST) and an online test are known. These methods provide each LSI with a function of testing for its proper operation. The BIST runs the LSI in test mode different from normal operation and checks for a fault. The online test checks for a fault during normal operation of the LSI. By these test functions, a fault existing in a logical design block of IP can be detected.